As a data output drive circuit provided to a semiconductor storage device, there is a proposal for a data output drive circuit corresponding to plural drive impedances. The data output drive circuit is provided with a driver that has an output impedance that is the lowest common multiple of the plural drive impedances, and a driver that has an output impedance that is a sub-multiple of the lowest common multiple, with these in a parallel layout, and a driver sets the parallel connections according to the drive impedance. In order to adjust the output impedance, the driver is formed with plural PMOS transistor pull-up drivers that are respectively connected to resistors, and with plural NMOS transistor pull-down drivers that are respectively connected to resistors.
However, in a semiconductor integrated circuit, the resistance values of transistors and resistors fluctuate due to variations in the manufacturing processes and to temperature fluctuations. There is a proposal as an interface circuit of a semiconductor integrated circuit for an interface circuit equipped with a calibration circuit for adjusting the ON resistance of transistors provided to the driver circuit. The interface circuit is equipped with a driver circuit that combines plural transistors, and an end terminal resistor. The calibration circuit uses a constant current source to detect changes in an ON resistance value of an N-channel MOSFET, in an ON resistance value of a P channel MOSFET, and in a resistance value of a resistor, and selectively switches ON plural transistors in the driver circuit based on the detection result. The interface circuit matches the overall resistance value of the transistor ON resistance and final terminal resistance of the driver circuit to the characteristic impedance of the transmission path so as not to vary with changes in the manufacturing processes and temperature fluctuations.
As an output buffer circuit that transmits a logical signal to the transmission path, there is a proposal for an output buffer circuit that applies pre-emphasis to a transmission output waveform in order to compensate for signal attenuation occurring in the transmission path. This output buffer circuit is provided with P-type transistors and N-type transistors that operated in a complementary manner to each other in plural respective buffer circuits, such that the output impedance is constant irrespective of the output voltage. By setting the output buffer circuit with a range in which the output impedance matches the characteristic impedance of the transmission path for each of the buffers, the output impedance of the output buffer circuit is matched to the characteristic impedance of the transmission path. The output buffer circuit is also provided with switches to the plural buffers, and to adjust the amount of pre-emphasis and the number of pre-emphasis taps, the number of buffers that are ON at the same time is limited so as to match the output impedance to the characteristic impedance of the transmission path.